Banyan23
Joined: 30 Jul 2013
Posts: 5
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 Posted: Tue Jul 30, 2013 2:18 pm Post subject: MCU test chip shows performance boost and power saving optio |
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Transistor technology developer SuVolta has manufactured an ARM Cortex-M series processor featuring its Deeply Depleted Channel (DDC) technology. The device, fabricated on a 65nm bulk planar cmos process, is said to show 'significant' speed gains and an associated power reduction.
Dr Mathew Wojko, the company's principal digital engineer, said: "Initially, you validate technologies by building things like ring oscillators. This is the next logical step and provides silicon confirmation of DDC technology."
The Cortex-M0 test was compared to a baseline 350MHz device from technology partner Fujitsu. "We ran our chip from a 0.9V supply," said Dr Wojko, "and saw a 50% improvement in power consumption. Matching the power consumption with a 1.1V supply saw a 35% performance boost, while a 1.2V supply brought a 55% performance increase."
SuVolta says that, by applying DDC technology, designers can choose which supply voltage to use with their chips. "Now we've proven this with an M0," Dr Wojko said, "it provides a good metric about how the technology might perform when applied to an SoC featuring an A9 or an A15 core."
According to SuVolta, it has six partners working with DDC technology, with some addressing the 20nm node.
* Meanwhile, SuVolta and UMC are working to integrate DDC technology into UMC's High-K Metal Gate (HKMG) high performance mobile (HPM) process.
"We expect to see promising results from the joint technology development to further validate the power and performance benefits of DDC technology in UMC's 28nm HKMG process," said TR Yew, vp of UMC's advanced technology division.
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